The use of floating gate technology in flash memory devices is well known. Typically, a Si channel of n or p type semiconductor is provided. The floating gate transistor is surrounded by oxide, enabling a charge stored on the gate to remain there. Program and erase operations take place by a process of channel injection. Electrons undergo Fowler-Nordheim (FN) tunneling and are transferred from the channel to the floating gate, and vice-versa, during operation.
To provide an efficient channel injection, the possibility of a gate injection (transfer of electrons between the control gate and floating gate via FN tunneling) must be reduced. This is accomplished by maximizing the gate coupling ratio. The gate coupling ratio (GCR) is defined as the ratio of floating gate potential to control gate potential. A GCR of 1 is optimal, but a GCR greater than 0.6 is sufficient for most flash memory devices.
This result is satisfactory for larger memory devices, but when these devices are scaled down, a high GCR becomes difficult to maintain. For NAND flash in particular, a GCR of less than 0.3 is predicted when the node is below 45 nm. The bottom tunnel oxide will not have a sufficiently large electric field to allow FN tunneling. Moreover, future flash memory devices will require FinFET-like structures to improve device short-channel characteristics. These structures have a naturally large channel to floating gate coupling capacitance, and thus a naturally low GCR.
Additionally, there is a problem of inter-floating gate coupling in traditional flash memory device arrays. Inter-floating gate coupling capacitance is comparable to the gate coupling capacitance of the channel and floating gate as the density of cells in the array becomes greater. This causes interference among the cells which deteriorates functionality of the flash memory device. Furthermore, electric field stress on the gate oxide affects reliability and endurance of the unit.
It is therefore desirable to operate the floating gate apparatus in such a way as to enable efficient FN tunneling to the floating gate, particularly when using a FinFET-like structure. It is also desirable to operate the floating gate apparatus in such a way as to increase reliability and endurance, and to reduce inter-cell interference as the devices are scaled down.